The present invention relates, in general, to electronics, and more particularly, to semiconductor package substrates, embedded trace substrates, and methods of forming embedded trace substrates having a finer line trace width with relatively higher interfacial bonding strength at a relatively lower cost.
Recently, packaged integrated circuit (IC) structures for mobile applications have become a main driver of the semiconductor industry. Small form factor, thin profile, high performance, multi-function integration and low cost are important requirements for mobile applications and have generated numerous developments in the process, materials, and equipment sectors. Some package solutions have been developed to meet these requirements including embedded trace substrates, which can provide a cost-effective alternative compared with other existing solutions. Compared to traditional core substrates, embedded trace substrates can simplify the substrate fabrication process and enable a finer line width capability in a cost effective manner.
FIGS. 1A through 1E show cross-sectional views of an embedded trace substrate at various stages of fabrication in accordance with the related art.
Referring to FIG. 1A, metal bump patterns 106a, 106b are formed on each of separation films 104a, 104b of a carrier 102. The separation films 104a, 104b are formed on an upper portion and a lower portion of the carrier 102 respectively.
Referring to FIG. 1B, dielectric films 107a and 107b having vias are formed on each of the metal bump patterns 106a, 106b to provide metal patterns connected to each of the metal bump patterns 106a, 106b. Embedded trace substrates 108a, 108b are thus formed on the upper portion and the lower portion of the carrier 102 respectively.
Next, the two embedded trace substrates 108a, 108b including the metal bump patterns 106a, 106b are stripped away from the carrier 102 as shown in FIG. 1C.
Next, as shown in FIG. 1D, a blanket front etching process is used to globally and non-selectively remove portions of the metal bump pattern 106a of the embedded trace substrate 108a. The front etching process is carried out sequentially until the upper portion of the dielectric film 107a is exposed. As shown in FIG. 1E, after the front etching process, bump pads 106 for the embedded pattern are formed. In accordance with the related process, the bump pads 106 are recessed approximately 5-7 micrometers or more below the top surface of the dielectric film 107a due to over-etching, which is difficult to control. The formation of bump pads 106 in this recessed or over-etched manner is one problem with the related embedded trace substrate manufacturing process that can lead to reliability problems. For example, bonding problems between a semiconductor chip and the bond pads 106a can occur because the bonding area is too thin and/or too small. This bonding problem can lead to reliability issues with the bonding interface and can contribute to the deterioration of the mechanical and electrical properties of the packaged device.
Accordingly, it is desired to have an alternative structure and method for providing embedded trace substrates that overcome, among other things, the issues of the related art. Also, it would be beneficial for such a structure and method to be cost effective and compatible with existing manufacturing processes.
For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote generally the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. It will be appreciated by those skilled in the art that words, during, while, and when as used herein related to circuit operation are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as propagation delay, between the reaction that is initiated by the initial action. Additionally, the term while means a certain action occurs at least within some portion of a duration of the initiating action. The use of word approximately or substantially means a value of an element is expected to be close to a state value or position. However, as is well known in the art there are always minor variances preventing values or positions from being exactly stated. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be understood that, although the terms first, second, etc. may be used herein to describe various members, elements, regions, layers and/or parts, these members, elements, regions, layers and/or parts are not be limited by these terms. These terms are only used to distinguish one member, element, region, layer and/or part from another member, element, region, layer and/or part. Thus, for example, a first member, element, region, layer and/or part discussed below could be termed a second member, element, region, layer and/or part without departing from the teachings of the present invention.